1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of Related Art
Upon forming a field effect transistor (FET) to a semiconductor device, an LDD (Lightly Doped Drain) region with addition of an impurity at a relatively low density (also referred to as an extension region) is sometimes formed to a source—drain region. This can suppress the short channel effect. Generally, the LDD region is formed by impurity implantation using a gate electrode as a mask.
For example, Patent Document 1 (Japanese Laid-Open Patent Application No. 2000-216373) describes a constitution of disposing an offset spacer on the side wall of a gate structure for controlling the formation of an LDD region.
In a case of using the offset spacer, when a silicon nitride film is used as a material for the offset spacer, since the silicon nitride film is made of a material of more intense stress compared with a silicon oxide film, this can particularly improve the performance of an n-type channel.
Usually, plural kinds of transistors such as transistors of different conduction types or transistors of different performances are formed on a semiconductor substrate. For forming plural kinds of transistors, impurity ions have to be implanted at different steps. For this purpose, a treatment of planting ions at a step while protecting the region for forming some transistors with a resist film, then removing the resist film, implanting ions in another step while protecting the region for forming other portion of transistors with a resist film, and then removing the resist film after the implantation of ions is conducted. Further, for forming various transistors, the extension regions the respective transistors are often formed by conducting ion implantation treatment for plural times.
However, a silicon nitride film involves a problem of causing film reduction upon removal of resist. Particularly, when an SPM (mixed solution of sulfuric acid and aqueous hydrogen peroxide) treatment is conducted, the film reduction occurs remarkably. In the offset spacer structure used in the process after the 90 nm node, when the width of the offset spacer formed to the gate side wall changes even by several Å for controlling the overlap length between the gate and the extension region, the transistor characteristics fluctuate greatly and a desired transistors can no more be obtained. Accordingly, for reducing the variation in manufacture, it is important to suppress the change of the film thickness of the offset spacer.
FIGS. 7a and 7b illustrate cross sectional views of a related art.
A semiconductor device 1 includes a semiconductor substrate 2, a gate insulation film 10 formed thereon, a gate electrode 12 formed on the gate insulation film 10, and an offset spacer 14 formed on the side wall of the gate electrode and constituted with a silicon nitride film (FIG. 7a). In a case of conducting ion implantation while once protecting a transistor formed in other region with a resist film and then the resist film is removed, film reduction is caused to the offset space 14 constituted with the silicon nitride film under the effect of the SPM treatment upon removal of the resist film (FIG. 7b). Particularly, the silicon nitride film is etched at an upper portion where it tends to be exposed to the chemical solution, which makes the offset spacer 14 into a tapered shape.
As has been described above, while the offset spacer 14 is provided for controlling the overlap length between the gate and the extension region, it requires a thickness to some extent, for example, a height of about 30 nm or more in order to function as an offset spacer. In a portion where the height of the offset spacer is not sufficient, ions pass and are injected into the semiconductor substrate 2 upon ion implantation. Accordingly, the overlap length between the gate and the extension region is not formed as designed. Accordingly, fine control of the transistor characteristic is difficult.
Patent Document 1 discloses a procedure of conducting an annealing treatment of a thin oxide at a temperature of about 800° C. for annealing the substrate and the gate structure after forming an offset spacer on the side wall of a gate structure. It is described that the offset spacer can protect the gate structure during a thin oxide annealing treatment to prevent formation of birds beak at the boundary between the gate oxide layer and the gate conductor layer.
However, in the technique described in Patent Document 1, a thin oxide annealing treatment is conducted at a high temperature (about 800° C.) after forming the offset spacer. Accordingly, in a case where a gate electrode is constituted for example with polysilicon and impurities are diffused in the polysilicon, diffusion of the impurities may possibly cause diffusion of the impurities between the N-type MOS region and the P-type MOS region to each other, or break through of the impurities through the gate electrode. This results in a problem of causing the diffusion of the impurities to deteriorate the characteristics of transistors.
Patent document 2 (Japanese Laid-Open Patent Application No. 2001-250944) describes a technique of forming a silicon nitride film so as to cover a polysilicon gate and applying a heat treatment in an oxidative atmosphere thereby forming a silicon oxynitride film, anisotropically etching the film to form a side wall in which the silicon nitride film and the silicon oxynitride film are stacked in this order. It is described that deposition of silicon pieces on the surface of the side wall can be prevented upon forming a selective silicon film of a predetermined thickness in a source—drain region by an epitaxial growing method.
However, this document 2 does not disclose a LDD structure. Therefore, the technology of this document 2 does not relate to a transistor having a LDD structure.